Field of the Invention
The present invention relates to computer systems using a bus bridge(s) to interface a central processor(s), video graphics processor(s), random access memory and input-output peripherals together, and more particularly, in utilizing a two-level cache having distributed first-level caches that are coupled to respective interfaces and a second-level cache that is commonly used by the first-level caches, the second-level cache being coupled to a memory controller for obtaining GART table entries from the computer system main memory when needed because of a cache miss in both the first-level and second-level caches.